View AM29F016-120SCB_393895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FINAL
Am29F016
16-Megabit (2,097,152 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 Volt 10% for read and write operations -- Minimizes system level power requirements s Compatible with JEDEC-standards -- Pinout and software compatible with single-power supply Flash -- Superior inadvertent write protection s 48-pin TSOP s 44-pin SO s Minimum 100,000 write/erase cycles guaranteed s High performance -- 70 ns maximum access time s Sector erase architecture -- Uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased. Also supports full chip erase s Group sector protection -- Hardware method that disables any combination of sector groups from write or erase operations (a sector group consists of 4 adjacent sectors of 64 Kbytes each) s Embedded Erase Algorithms -- Automatically pre-programs and erases the chip or any sector s Embedded Program Algorithms -- Automatically programs and verifies data at specified address s Data Polling and Toggle Bit feature for detection of program or erase cycle completion s Ready/Busy output (RY/BY) -- Hardware method for detection of program or erase cycle completion s Erase Suspend/Resume -- Supports reading or programming data to a sector not being erased s Low power consumption -- 25 mA typical active read current -- 30 mA typical program/erase current s Enhanced power management for standby mode -- <1 A typical standby current -- Standard access time from standby mode s Hardware RESET pin -- Resets internal state machine to the read mode
GENERAL DESCRIPTION
The Am29F016 is a 16 Mbit, 5.0 Volt-only Flash memory organized as 2 Megabytes of 8 bits each. The 2 Mbytes of data is divided into 32 sectors of 64 Kbytes for flexible erase capability. The 8 bits of data appear on DQ0-DQ7. The Am29F016 is offered in 48-pin TSOP and 44-pin SO packages. This device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. 12.0 Volt V PP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard Am29F016 offers access times of 70 ns, 90 ns, 120 ns, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The Am29F016 is entirely command set compatible with the JEDEC single-power supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 Volt Flash or EPROM devices. The Am29F016 is programmed by executing the program command sequence. This will invoke the EmbedPublication# 18805 Rev: D Amendment/0 Issue Date: April 1997
ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within one second. The Am29F016 is erased when shipped from the factory. The Am29F016 device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. A sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31. AMD has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from, or program data to, a sector that was not being erased. Thus, true background erase can be achieved. The device features single 5.0 Volt power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the RY/BY pin, Data Polling of DQ7, or by the Toggle Bit I (DQ6).Once the end of a program or erase cycle has been completed, the device automatically resets to the readmode. The Am29F016 also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm will be terminated. The internal state machine will then be reset into the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device will be automatically reset to the read mode. This will enable the system's microprocessor to read the boot-up firmware from the Flash memory. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t effectiveness. The Am29F016 memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s Thirty two 64 Kbyte sectors s Eight sector groups each of which consists of 4 adjacent sectors in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31. s Individual-sector or multiple-sector erase capability s Sector group protection is user-definable
SA31 SA30 SA29 SA28 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh 000000h
Sector Group 7
32 Sectors Total
SA3 SA2 SA1 SA0
64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte
Sector Group 0
18805D-1
2
Am29F016
PRODUCT SELECTOR GUIDE
Family Part No. Ordering Part No: VCC = 5.0 Volt 5% VCC = 5.0 Volt 10% Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) 70 70 40 -75 -90 90 90 40 -120 120 120 50 -150 150 150 75
BLOCK DIAGRAM
DQ0-DQ7 VCC VSS RY/BY RESET State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
WE
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE OE
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A20
18805D-2
Am29F016
3
CONNECTION DIAGRAMS
SO
NC RESET A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VCC CE A12 A13 A14 A15 A16 A17 A18 A19 NC NC A20 NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC
18805D-3A
4
Am29F016
CONNECTION DIAGRAMS
NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE VCC NC RESET A11 A10 A9 A8 A7 A6 A5 A4 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard TSOP
18805D-3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC A20 NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC
NC NC A20 NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE VCC NC RESET A11 A10 A9 A8 A7 A6 A5 A4 NC NC
18805D-4
Am29F016
5
PIN CONFIGURATION
A0-A20 CE NC OE RESET RY/BY VCC = 21 Addresses = Chip Enable = Pin Not Connected Internally = Output Enable = Hardware Reset Pin, Active Low = Ready/BUSY Output = +5.0 Volt Single-Power Supply (10% for -90, -120, -150) or (5% for -95) = Device Ground = Write Enable
LOGIC SYMBOL
21 A0-A20 DQ0-DQ7 8
DQ0-DQ7 = 8 Data Inputs/Outputs
CE (E) OE (G) WE (W) RESET RY/BY
VSS WE
18805D-5
6
Am29F016
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:
AM29F016
-75
E
I
B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am29F016 16 Megabit (2M x 8-Bit) CMOS Flash Memory 5.0 Volt-only Program and Erase
Valid Combinations AM29F016-75 EC, EI, FC, FI, SC, SI AM29F016-90 AM29F016-120 AM29F016-150 EC, ECB, EI, EIB, FC, FCB, FI, FIB, SC, SCB, SI, SIB
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am29F016
7
Table 1.
Operation Autoselect, AMD Manuf. Code (1) Autoselect Device Code (1) Read Standby Output Disable Write Enable Sector Group Protect (2) Verify Sector Group Protect (2) Temporary Sector Group Unprotect Hardware Reset/Standby CE L L L H L L L L X X
Am29F016 User Bus Operations
OE L L L X H H VID L X X WE H H X X H L L H X X A0 L H A0 X X A0 X L X X A1 L L A1 X X A1 X H X X A6 L L A6 X X A6 X L X X A9 VID VID A9 X X A9 VID VID X X DQ0-DQ7 Code Code DOUT HIGH Z HIGH Z DIN X Code X HIGH Z RESET H H H H H H H H VID L
Legend: L = logic 0, H = logic 1, X = Don't Care. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5. 2. Refer to the section on Sector Group Protection.
Read Mode
The Am29F016 has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if the device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time). reduced to less than 1 A. A TTL standby mode is achieved with CE and RESET pins held at VIH. Under this condition the current is typically reduced to 200 A. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = don't care). Under this condition the current is typically reduced to less than 1 A. A TTL standby mode is achieved with RESET pin held at VIL (CE = don't care). Under this condition the current is typically reduced to less than 200 A. Once the RESET pin is taken high, the device requires 50 ns of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
Standby Mode
There are two ways to implement the standby mode on the Am29F016 device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current is typically
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
8
Am29F016
Autoselect
The autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6 (seeTable 2). The manufacturer and device codes may also be read via the command register, for instances when the Am29F016 is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table 5 (see Autoselect Command Sequence). Byte 0 (A0 = VIL) represents the manufacturer's code (AMD = 01H) and byte 1 (A0 = VIH) the device identifier code for Am29F016 = ADH. These two bytes are given in the table below. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL (see Table 2). The autoselect mode also facilitates the determination of sector group protection in the system. By performing a read operation at the address location XX02H with the higher order address bits A18, A19, and A20 set to the desired sector group address, the device will return 01H for a protected sector group and 00H for a non-protected sector group.
Table 2. Am29F016 Sector Protection Verify Autoselect Codes
Type Manufacturer Code-AMD Am29F016 Device Sector Group Protection A18 to A20 X X X X X X A6 VIL VIL VIL A1 VIL VIL VIH A0 VIL VIH VIL Code DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 (HEX) 01H ADH 01H* 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1
Sector Group Address
* Outputs 01H at protected sector addresses
Am29F016
9
Table 3.
A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Sector Address Table
A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh
10
Am29F016
Table 4. Sector Group Addresses
A20 SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 0 0 0 0 1 1 1 1 A19 0 0 1 1 0 0 1 1 A18 0 1 0 1 0 1 0 1 Sectors SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. It is possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order address bits A18, A19, and A20 is the desired sector group address, will produce a logical "1" at DQ0 for a protected sector group. See Table 2 for Autoselect codes.
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups of the Am29F016 device in order to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET pin to high voltage (12V). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 15 and 16.
Sector Group Protection
The Am29F016 features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see Table 4). The sector group protect feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. Alternatively, AMD may program and protect sector groups in the factory prior to shipping the device (AMD's ExpressFlashTM Service).
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read mode.
Am29F016
11
Table 5.
Command Sequence Read/Reset Reset/Read Reset/Read Autoselect Byte Program Chip Erase Sector Erase Erase Suspend Erase Resume Bus Write Cycles Req'd 1 3 3 4 6 6 1 1 First Bus Write Cycle Addr XXXXH 5555H 5555H 5555H 5555H 5555H XXXXH XXXXH Data F0H AAH AAH AAH AAH AAH B0H 30H
Am29F016 Command Definitions
Second Bus Write Cycle Addr Data Third Bus Write Cycle Addr Data Fourth Bus Read/Write Cycle Addr Data Fifth Bus Write Cycle Addr Data Sixth Bus Write Cycle Addr Data
2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
55H 55H 55H 55H 55H
5555H 5555H 5555H 5555H 5555H
F0H 90H A0H 80H 80H
RA
RD
PA 5555H 5555H
Data AAH 2AAAH 55H 5555H AAH 2AAAH 55H SA 10H 30H
Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA= Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select any sector. 3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 4. Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode. 5. Address bits A15, A14, A13, A12 and A11 = X, X = don't care.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacturer code of 01H. A read cycle from address XX01H returns the device code ADH (see Table 2). All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Furthermore, the write protect status of sectors can be read in this mode. Scanning the sector group addresses (A18, A19, and A20) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Autoselect Command
Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an autoselect command operation to supplement traditional PROM programming
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming using the Embedded Program Algo-
12
Am29F016
rithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. This automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see Table 6, Write Operation Status). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 1 illustrates the Embedded Programming Algor ithm using typic al command s tr ings and bus operations.
then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (30H) is latched on the rising edge of WE. After a time-out of 50 s from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 s from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 s time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this period will reset the device to the read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete.(Refer to the Write Operation Status section for DQ3, Sector Erase Timer, operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 31). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" (see Write Operation Status section) at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to read mode. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are
Am29F016
13
Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are "don't-cares" when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 s to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin and the DQ7 bit will be at logic `1', and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-sus-
pended. Successively reading from the erase-susp e n d e d s e c t o r w h i l e t h e d ev i c e i s i n t h e erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2). After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-susp e n d e d s e c t o r w h i l e t h e d ev i c e i s i n t h e erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended program operation is detected by the RY/BY output pin, Data Polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from the byte program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
14
Am29F016
Write Operation Status
Table 6.
Status Byte Program in Embedded Program Algorithm Embedded Program Algorithm Erase Suspended Read In Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspended Read (Non-Erase Suspended Sector) Erase Suspended Read (Non-Erase Suspended Sector) Byte Program in Embedded Program Algorithm Exceeded Time Limits Program/Erase Program in Embedded Program Algorithm Erase Suspended Mode Erase Suspended Read (non-Erase Suspended Sector)
Write Operation Status
DQ7 DQ7 0 1 DQ6 Toggle Toggle 1 DQ5 0 0 0 DQ3 0 1 1 DQ2 1 Toggle Toggle (Note 1) Data 1 (Note 3) 1 N/A N/A
Data
Data Toggle (Note 2) Toggle Toggle Toggle
Data
Data
DQ7 DQ7 0 DQ7
0 1 1 1
1 0 1 1
Notes: 1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle. 2. Performing successive read operations from any address will cause DQ6 to toggle. 3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic `1' at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
DQ7
Data Polling The Am29F016 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 3. Data Polling will also flag the entry into Erase Suspend. DQ7 will switch "0" to "1" at the start of the Erase Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase Suspend Mode. During Program in Erase Suspend, Data Polling will perform the same as in regular program execution outside of the suspend mode. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector addresses within any of the sectors being erased and not a sector that is within a protected sector group. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 can be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out (see Table 6). See Figure 11 for the Data Polling timing specifications and diagrams.
Am29F016
15
DQ6
Toggle Bit I The Am29F016 also features the "Toggle Bit I" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 12 for the Toggle Bit I timing specifications and diagrams. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 6: Write Operation Status.
DQ2
Toggle Bit II This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspend sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic `1' at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard Program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows:
Mode Program Erase Erase Suspend Read (1) (Erase-Suspended Sector) Erase Suspend Program DQ7 DQ7 0 1 DQ7 (2) DQ6 toggles toggles 1 toggles DQ2 1 toggles toggles 1 (2)
DQ5
Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 1. The DQ5 failure condition will also appear if a user tries to program a "1" to a location that is previously programmed to "0". In this case the device locks out and never completes the Embedded Program Algorithm. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device.
DQ3
Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence.
Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended. 2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while DQ6 does not). See also Table 6 and Figure 17.
16
Am29F016
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy The Am29F016 provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the Am29F016 is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to Figure 13 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system's microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The Am29F016 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for V CC less than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V.
RESET
Hardware Reset The Am29F016 device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 s after the RESET pin is driven low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the RESET pin is taken high, the device requires 500 ns of wake up time until outputs are valid for read access.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V IL and OE = V IH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
Am29F016
17
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (see below)
Data Poll Device
Increment Address
No Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
18805D-6
Figure 1. Embedded Programming Algorithm
18
Am29F016
EMBEDDED ALGORITHMS
Start Write Erase Command Sequence (see below) Data Polling or Toggle Bit I Successfully Completed
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands are optional
Sector Address/30H
18805C-7
To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.
Figure 2. Embedded Erase Algorithm
Am29F016
19
Start
Read Byte (DQ0-DQ7) Addr = VA
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any non-protected sector group address during chip erase
Yes DQ7 = Data ? No No DQ5 = 1 ? Yes Yes Read Byte (DQ0-DQ7) Addr = VA
DQ7 = Data ? No Fail
Yes
Pass
18805D-8
DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 3. Data Polling Algorithm
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
18805D-10
Figure 5. Maximum Negative Overshoot Waveform
20
Am29F016
Start
Read Byte (DQ0-DQ7) Addr = Don't Care
No DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Yes Read Byte (DQ0-DQ7) Addr = Don't Care
No DQ6 = Toggle ? Yes Fail Pass
DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1".
18805D-9
Figure 4. Toggle Bit I Algorithm
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
18805D-11
Figure 6. Maximum Positive Overshoot Waveform
Am29F016
21
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground All pins except A9 (Note 1). . . . . . . . .-2.0 V to +7.0 V VCC (Note 1). . . . . . . . . . . . . . . . . . . .-2.0 V to +7.0 V A9, OE, RESET (Note 2) . . . . . . . . .-2.0 V to +13.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9, OE, RESET pins is -0.5 V. During voltage transitions, A9, OE, RESET pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the de-
vice to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Case Temperature (TC). . . . . . . . . . . . . .0C to +70C Industrial (I) Devices Case Temperature (TC). . . . . . . . . . . .-40C to +85C VCC Supply Voltages VCC for Am29F016-75 . . . . . . . . . +4.75 V to +5.25 V VCC for Am29F016-90, 120, 150. . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
22
Am29F016
DC CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current (Note 1) VCC Active Current (Notes 2, 3) VCC Standby Current VCC Standby Current (Reset) Input Low Level Input High Level Voltage for Autoselect and Sector VCC = 5.0 Volt Protect Output Low Voltage Output High Level Low VCC Lock-out Voltage IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA VCC = VCC Min 2.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.0 Volt VOUT = VSS to VCC, VCC = VCC Max CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, CE = VIH, RESET = VIH VCC = VCC Max, RESET = VIL -0.5 2.0 11.5 Min Max 1.0 50 1.0 40 60 1.0 1.0 0.8 VCC + 0.5 12.5 0.45 Unit A A A mA mA mA mA V V V V V V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested.
Am29F016
23
DC CHARACTERISTICS (continued) CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 VOH2 VLKO Low VCC Lock-out Voltage Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current (Note 1) VCC Active Current (Notes 2, 3) VCC Standby Current VCC Standby Current (Reset) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage VCC = 5.0 Volt IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min 0.85 VCC VCC - 0.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.0 Volt VOUT = VSS to VCC, VCC = VCC Max CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max, RESET = VSS 0.3 V -0.5 0.7 x VCC 11.5 25 30 1 1 Min Typ Max 1.0 50 1.0 40 40 5 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA A A V V V V V V V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested.
24
Am29F016
AC CHARACTERISTICS Read-only Operations Characteristics
Parameter Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tCE tOE tDF tDF tOH tReady Parameter Description Read Cycle Time 4 Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 3, 4) Output Enable to Output High Z (Notes 3, 4) Output Hold Time From Addresses CE or OE Whichever Occurs First RESET Pin Low to Read Mode 4 CE = VIL OE = VIL OE = VIL Test Setup Min Max Max Max Max Max Min Max Speed Options (Notes 1 and 2) -75 70 70 70 40 20 20 0 20 -90 90 90 90 40 20 20 0 20 -120 120 120 120 50 30 30 0 20 -150 150 150 150 55 35 35 0 20 Unit ns ns ns ns ns ns ns s
Notes: 1. Test Conditions (for -75): Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level: 1.5 V input and output
2. Test Conditions (for all others): Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level: 0.8 V and 2.0 V input and output 3. Output driver disable time. 4. Not 100% tested.
5.0 Volt IN3064 or Equivalent
2.7 k
Device Under Test CL
6.2 k Diodes = IN3064 or Equivalent
Note: CL (for -75) = 30 pF including jig capacitance CL (for all others) = 100 pF including jig capacitance
18805D-11
Figure 7. Test Conditions
Am29F016
25
AC CHARACTERISTICS Write/Erase/Program Operations
Parameter Symbol JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Standard tWC tAS tAH tDS tDH tOEH Parameter Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time Read 2 Toggle Bit I and Data Polling 2 Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ tWHWH2 tWHWH2 tVCS tVIDR tVLHT tOESP tRP tBUSY Sector Erase Operation 1 Max VCC Set Up Time 2 Rise Time to VID (Notes 2, 3) Voltage Transition Time (Notes 2, 3) OE Setup Time to WE Active (Notes 2, 3) RESET Pulse Width Program/Erase Valid to RY/BY Delay Min Min Min Min Min Min 8 50 500 4 4 500 40 8 50 500 4 4 500 40 8 50 500 4 4 500 50 8 50 500 4 4 500 60 sec s ns s s ns ns Speed Options (Notes 1 and 2) -75 70 0 40 40 0 0 10 0 0 0 40 20 7 1 -90 90 0 45 45 0 0 10 0 0 0 45 20 7 1 -120 120 0 50 50 0 0 10 0 0 0 50 20 7 1 -150 150 0 50 50 0 0 10 0 0 0 50 20 7 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns s sec
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1
tGHWL tCS tCH tWP tWPH tWHWH1
Read Recover Time Before Write (OE high to WE low) CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation
Notes: 1. This does not include the preprogramming time. 2. Not 100% tested. 3. These timings are for Temporary Sector Group Unprotect operation.
26
Am29F016
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST WAVEFORM
tRC Addresses tACC CE tOE OE (tDF) Addresses Stable
tOEH WE (tCE) (tOH)
Outputs
High Z Output Valid
High Z
18805D-12
Figure 8. AC Waveforms for Read Operations
Am29F016
27
SWITCHING WAVEFORMS
3rd Bus Cycle Addresses 5555H tWC CE tGHWL OE tWP WE tCS Data tDS 5.0 Volt tCE tWPH tDH A0H PD DQ7 DOUT tOH tOE tDF tWHWH1 PA tAS tAH Data Polling PA tRC
Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
18805D-13
Figure 9. Program Operation Timings
tAH Addresses 5555H 2AAAH tAS CE tGHWL OE tWP WE tCS Data AAH tDS VCC tVCS 55H 80H AAH 55H 10H/30H tWPH tDH 5555H 5555H 2AAAH SA
Note: SA is the sector address for Sector Erase. Addresses = don't care for Chip Erase.
18805D-14
Figure 10.
AC Waveforms Chip/Sector Erase Operations
28
Am29F016
SWITCHING WAVEFORMS
tCH tDF
CE
tOE OE tOEH WE tCE tOH
*
DQ7 tWHWH 1 or 2 DQ0-DQ6 DQ0-DQ6 = Invalid
DQ0-DQ7 Valid Data
DQ7
DQ7 = Valid Data
High Z
*DQ7 = Valid Data (The device has completed the Embedded operation).
18805D-15
Figure 11.
AC Waveforms for Data Polling During Embedded Algorithm Operations
CE tOEH WE
OE
*
Data (DQ0-DQ7) DQ6 = Toggle DQ6 = Toggle tOE DQ6 = Stop Toggling DQ0-DQ7 Valid
*DQ6 stops toggling (The device has completed the Embedded operation).
18805D-16
Figure 12. AC Waveforms for Toggle Bit I During Embedded Algorithm Operations
Am29F016
29
CE The rising edge of the last WE signal WE Entire programming or erase operations
RY/BY tBUSY
18805D-17
Figure 13.
RY/BY Timing Diagram During Program/Erase Operations
RESET
tRP tReady
18805D-18
Figure 14.
RESET Timing Diagram
Start
RESET = VID (Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotect Completed (Note 2)
18805D-21
Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again.
Figure 15.
Temporary Sector Group Unprotect Algorithm
30
Am29F016
12V
RESET CE
0 or 5V tVIDR
0V or 5 V
WE
Program or Erase Command Sequence RY/BY
18805D-22
Figure 16. Temporary Sector Group Unprotect Timing Diagram
Enter Embedded Erasing WE
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Toggle DQ2 and DQ6 with OE
Note: DQ2 is read from the erase-suspended sector.
18805D-23
Figure 17.
DQ2 vs. DQ6
Am29F016
31
AC CHARACTERISTICS Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter Symbol JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Standard tWC tAS tAH tDS tDH tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Parameter Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Address Hold Time Output Enable Setup Time (Note 2) Output Enable Hold Time Read (Note 2) Toggle Bit I and Data Polling (Note 2) Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Sector Erase Operation (Note 1) Max 8 8 8 8 sec Speed Options (Notes 1 and 2) -75 70 0 40 40 0 0 0 10 0 0 0 40 20 7 1 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 1 -120 120 0 50 50 0 0 0 10 0 0 0 50 20 7 1 -150 150 0 50 50 0 0 0 10 0 0 0 50 20 7 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s sec
Read Recover Time Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation
Notes: 1. This does not include the preprogramming time. 2. Not 100% tested.
32
Am29F016
Data Polling Addresses 5555H tWC WE tGHEL OE tCP CE tWS tCPH tDH Data tDS 5.0 Volt A0H PD DQ7 DOUT tWHWH1 PA tAS tAH PA
Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
18805D-24
Figure 18.
Alternate CE Controlled Program Operation Timing
Am29F016
33
ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Min Typ 1 (Note 1) 32 7 Max 8 256 300 (Note 3) Unit sec sec s sec Comments Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Excludes system-level overhead Excludes system-level overhead
14.4 (Note 1) 43.2 (Notes 2, 3)
Notes: 1. 25C, 5 V VCC, 100,000 cycles. 2. Although Embedded Algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 3. Under worst case condition of 90C, 4.5 V VCC, 100,000 cycles.
LATCHUP CHARACTERISTIC
Min Input Voltage with respect to VSS on I/O pins VCC Current -1.0 V -100 mA Max VCC + 1.0 V +100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance VIN = 0 VOUT = 0 VIN = 0 Test Conditions Min 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
34
Am29F016
PHYSICAL DIMENSIONS TS 048 48-Pin Standard Thin Small Outline Package
0.95 1.05 Pin 1 I.D.
1 48
11.90 12.10
0.50 BSC
24 25
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0.25MM (0.0098") BSC 0 5 0.50 0.70
16-038-TS48-2 TS 048 DA101 8-8-94 ae
Am29F016
35
PHYSICAL DIMENSIONS TSR048 48-Pin Reversed Thin Small Outline Package
0.95 1.05 Pin 1 I.D.
1 48
11.90 12.10
0.50 BSC
24 25
18.30 18.50 19.80 20.20 SEATING PLANE
0.05 0.15
1.20 MAX 0.25MM (0.0098") BSC 0 5 0.50 0.70
0.08 0.20 0.10 0.21
16-038-TS48 TSR048 DA104 8-8-94 ae
Trademarks Copyright (c) 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies
36
Am29F016

▲Up To Search▲

Price & Availability of AM29F016-120SCB

	To Download AM29F016-120SCB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .